数字逻辑电路学习指导 2020秋数字逻辑电路06班 11.11功能扩展专题 61 11.11.1本质 61 11.11.2“黑盒子”模型一解题方法 61 11.11.3以一道作业题目为例 63 11.12数制和码制例题补充 65 11.12.1十进制码和格雷码的转换 。。。。4。 65 11.12.2二进制码和BCD码的转换 65 11.13逻辑代数基础例题补充 66 11.13.1异或运算和同或运算 66 11.13.2利用公共项实现最简逻辑函数式 66 11.13.3无关项在化简中的应用 66 11.14加法器的应用 67 11.14.1加法器实现加减运算 。。。。。 67 11.14.2加法器实现乘法运算 67 11.15有限制的功能扩展问题 68 12第五章至第八章经典问题综合整理 70 12.1SR锁存器的约束条件与“不定”状态的理解 70 12.1.1简述… 70 121.2SR锁存器电路结构与特性表 70 12.1.3SR锁存器约束条件与“不定”状态的解读 71 12.2触发器的逻辑功能和触发方式 72 12.2.1简介 72 12.2.2逻辑功能和触发方式的关系 72 12.2.3关于逻辑功能 73 12.3触发器的异步置位问题 73 12.3.1简介… 73 12.3.2怎么识别是同步输入还是异步输入 73 12.3.3只有一个Sp或者RD 74 12.3.4异步输入对主从触发器如何影响 75 12.4触发器的动态特性 75 12.4.1简介 75 12.4.2考察要求和如何学习 76 4数字逻辑电路学习指导 2020 秋数字逻辑电路 06 班 11.11 功能扩展专题 ·········································································· 61 11.11.1 本质 ·············································································· 61 11.11.2 “黑盒子”模型——解题方法 ············································· 61 11.11.3 以一道作业题目为例 ························································· 63 11.12 数制和码制例题补充 ································································· 65 11.12.1 十进制码和格雷码的转换 ··················································· 65 11.12.2 二进制码和 BCD 码的转换 ················································· 65 11.13 逻辑代数基础例题补充 ······························································ 66 11.13.1 异或运算和同或运算 ························································· 66 11.13.2 利用公共项实现最简逻辑函数式 ·········································· 66 11.13.3 无关项在化简中的应用 ······················································ 66 11.14 加法器的应用 ·········································································· 67 11.14.1 加法器实现加减运算 ························································· 67 11.14.2 加法器实现乘法运算 ························································· 67 11.15 有限制的功能扩展问题 ······························································ 68 12 第五章至第八章经典问题综合整理 ························································· 70 12.1 SR 锁存器的约束条件与“不定”状态的理解 ··································· 70 12.1.1 简述 ················································································ 70 12.1.2 SR 锁存器电路结构与特性表 ················································ 70 12.1.3 SR 锁存器约束条件与“不定”状态的解读 ······························ 71 12.2 触发器的逻辑功能和触发方式 ······················································· 72 12.2.1 简介 ················································································ 72 12.2.2 逻辑功能和触发方式的关系 ·················································· 72 12.2.3 关于逻辑功能 ···································································· 73 12.3 触发器的异步置位问题 ································································ 73 12.3.1 简介 ················································································ 73 12.3.2 怎么识别是同步输入还是异步输入 ········································ 73 12.3.3 只有一个 SD 或者 RD ························································· 74 12.3.4 异步输入对主从触发器如何影响 ··········································· 75 12.4 触发器的动态特性 ······································································ 75 12.4.1 简介 ················································································ 75 12.4.2 考察要求和如何学习 ··························································· 76 4