Abstract Abstract With the development of SOC and mixed-signal circuits,the research on the interfaces between the digital and analog domains becomes more and more important.Within these interfaces,we find the analog-to-digital converter (ADC)and digital-to-analog converter(DAC).These data converters are not only used for conversion of audio via microphone or loudspeakers,video via camera or display,into information that the computer or digital signal processor (DSP)can handle.The data converters are also used for data transmission via a channel,where the channel is either wireline or wireless(radio).Typically, the data(signal)is modulated onto a carrier according to some scheme.The signal is then sent over the channel with the carrier.The receiver will demodulate and extract the data (signal).The modulation can be done in both the digital and analog domain dependent on application and feasibility. In high-speed data conversion circuit,speed,accuracy,power dissipation and chip area are four key performance specifications.They are not independent;instead,they are interrelated and limit each other.There is always a trade-off among these four aspects. This thesis mainly focuses on the design and simulation of the 10-bit 100MSample/s current-steering DAC.The DAC has a"6+2+2"segmented architecture:first,the six most significant bits(MSB's)are thermometer decoded;second,the intermediate two bits are also thermometer decoded,but independently from the MSB's;third,the two least significant bits (LSB's)are binary weighted.Latch is used to synchronize the switching control signals,and then control the current through the load.The segmented architecture has an advantage of achieving a good glitch energy.The glitch energy is reduced to 0.436pV.s.Besides,the current source using cascoded PMOS transistors improves the resolution. KEY WORDS-DAC;Segmented Architecture;Thermometer decoded; Binary decoded;Current Source;Switch;Latch;Glitch.Abstract Abstract With the development of SOC and mixed-signal circuits, the research on the interfaces between the digital and analog domains becomes more and more important. Within these interfaces, we find the analog-to-digital converter (ADC) and digital-to-analog converter(DAC). These data converters are not only used for conversion of audio via microphone or loudspeakers, video via camera or display, into information that the computer or digital signal processor (DSP) can handle. The data converters are also used for data transmission via a channel, where the channel is either wireline or wireless (radio). Typically, the data (signal) is modulated onto a carrier according to some scheme. The signal is then sent over the channel with the carrier. The receiver will demodulate and extract the data (signal). The modulation can be done in both the digital and analog domain dependent on application and feasibility. In high-speed data conversion circuit, speed, accuracy, power dissipation and chip area are four key performance specifications. They are not independent; instead, they are interrelated and limit each other. There is always a trade-off among these four aspects. This thesis mainly focuses on the design and simulation of the 10-bit 100MSample/s current-steering DAC. The DAC has a “6+2+2” segmented architecture: first, the six most significant bits (MSB’s) are thermometer decoded; second, the intermediate two bits are also thermometer decoded, but independently from the MSB’s; third, the two least significant bits (LSB’s) are binary weighted. Latch is used to synchronize the switching control signals, and then control the current through the load. The segmented architecture has an advantage of achieving a good glitch energy. The glitch energy is reduced to 0.436pVis. Besides, the current source using cascoded PMOS transistors improves the resolution. KEY WORDS — DAC; Segmented Architecture; Thermometer decoded; Binary decoded; Current Source; Switch; Latch; Glitch