●文本编辑法 library ieee useieee.std_logic_1164.all; useieee. std _logic_unsigned. all; entity rsis port(r, s in std _logic q, qn: out std lo gic) end rs: architecture one ofrs is signal q1, qn1: std logic; begin gin q1<-s nand qn qn1 <=rand q1; q<=q1 gns=gn end one;⚫文本编辑法 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RS is port(r,s:in std_logic; q, qn: out std_logic); end RS; architecture one of RS is signal q1,qn1: std_logic; begin q1<=s nand qn1; qn1 <= r nand q1; q<=q1; qn <= qn1; end one;