Digltal Design and Computer Architecture with full hazard handling 图7.58 CLK CLK CLK RegWriteD RegWriteE Control MemtoRegD MemtoRegE MemtoRegM MemtoRegW unit MemWriteD MemWriteE MemWriteM ALUControlDo ALUControlE2o 3120 Op ALUSrcD ALUSrcE 5:0 Funct RegDstD RegDstE BranchD CLK CLK EqualD CLK CLK 2521 WE3 WE RD Instro A1 RD1 1 ALUOutM ReadDataW Instruction A RD 20:16 memory A2 RD2 SrcBE Data A3 1 WD3 Register WriteDataE WriteDataM memory file WD 2521 RsD RsE ALUOutW 20:16 RtD RdE RdE WriteRegE WriteRegM. 1511 Sign SignlmmD 150 extend <<2 PCPlus4F PCPlus4D PCBranchD BranchD ForwardAD Forward BO ForwardAE ForwardBE MemtoRegE RegWriteE emto RegM Hazard unitwith full hazard handling 图7.58