DLX(MIPS)数据通路一种简单实现 Instruction:工ns↑r. Decode氵 Execute Memory Write Fetch Reg. Fetch氵Addr.calc氵 Access氵Back Next pc Next SEQ PC Zero? RS1 RS2元 3o WB Data 中国科学技术大学 chapter3. 15中国科学技术大学 chapter3.10 DLX(MIPS)数据通路一种简单实现 Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc L M D ALU MUX Memory Reg File MUX MUX Data Memory MUX Sign Extend 4 Adder Zero? Next SEQ PC Address Next PC WB Data Inst RD RS1 RS2 Imm