Timing Control always @(posedge clk)q d; Waiting for an event initial begin #10 Running until they a=1;b=0; encounter a delay #10 <a=0;b=1; end Can not be synthesis！ initial begin wait(reset); Waiting for an event a=0; end 2021/1/13 ASIC Design,by Yan Bo 13ASIC Design, by Yan Bo Timing Control initial begin #10 a = 1; b = 0; #10 a = 0; b = 1; end always @(posedge clk) q = d; initial begin wait(reset); a = 0; end Running until they encounter a delay Waiting for an event Waiting for an event 2021/1/13 13 Can not be synthesis!