Abstract The thesis presents the design of a 3.3V 100MHz 10-bit pipeline Analog-to-Digital Convert following an analysis on various high speed A/D convert. It's a 1.5bit/stage pipeline ADC with 9 stages.Besides,the following technologies are taken:high-speed,high-gain OTA and improved bootstrap sample switches used in S/H,resulting in higher resolution and higher linearity;the dynamic comparators which are lack of kickback noise keep the analog signal from pipeline stage stable during the high frequency sampling phase:the two-phase non-overlapping clock generator is designed to make full use of the holding time.A proposed stable high-swing bias circuit is used for a wide-swing gain-boosting telescopic amplifier to improve the performance. In order to decrease the power of the whole chip,the telescopic architecture amplifier is used,which need least power of three traditional amplifiers,furthermore,the dynamic comparators help to decrease the power and the amplifer in each stage is scaled down gradually. This chip is being manufactured in Charter 0.35um double-poly four-metal CMOS mixed-signal process.The consumed die area is 1.2X1.1mm'. The power dissipation is 142mW with 3.3v power supply.SNDR is 58.7dB when sampling 42MHz sinusoid input signal at 100MHz sampling clock.Abstract The thesis presents the design of a 3.3V 100MHz 10-bit pipeline Analog-to-Digital Convert following an analysis on various high speed A/D convert. It’s a 1.5bit/stage pipeline ADC with 9 stages. Besides, the following technologies are taken: high-speed, high-gain OTA and improved bootstrap sample switches used in S/H, resulting in higher resolution and higher linearity; the dynamic comparators which are lack of kickback noise keep the analog signal from pipeline stage stable during the high frequency sampling phase; the two-phase non-overlapping clock generator is designed to make full use of the holding time. A proposed stable high-swing bias circuit is used for a wide-swing gain-boosting telescopic amplifier to improve the performance. In order to decrease the power of the whole chip, the telescopic architecture amplifier is used, which need least power of three traditional amplifiers, furthermore, the dynamic comparators help to decrease the power and the amplifer in each stage is scaled down gradually. This chip is being manufactured in Charter 0.35um double-poly four-metal CMOS mixed-signal process. The consumed die area is 1.2×1.1mm2 . The power dissipation is 142mW with 3.3v power supply. SNDR is 58.7dB when sampling 42MHz sinusoid input signal at 100MHz sampling clock. II