ce- based asic设计流程 ●基于标准单元的半定制设计流程 Venlo VHDL Tape out synthesis Post layout simulaton DRC LVS netlist GDSII Place route Routed on Institute of Microelectronics, Peking University 集成电路设计实习一单元实验四 Copyright◎2011-2012 数字系统设计Institute of Microelectronics, Peking University Copyright © 2011-2012 集成电路设计实习－单元实验四 数字系统设计 Page 3 Cell-based ASIC 设计流程 基于标准单元的半定制设计流程