EDA技术讲义 【例】D触发器的ⅤHDL语言描述 LIBRARY IEEE USE IEEE STD LOGIC 1164ALL entitY ddfs PORT(CLK: IN STD LOGIC i D: IN STD LOGIC i Q, QD: OUT STD LOGIC ) end ddf ARChiteCTuRE ex of ddf is BEGINEDA技术讲义 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY ddf IS PORT (CLK : IN STD_LOGIC ; D : IN STD_LOGIC ; Q, QD: OUT STD_LOGIC ); END ddf; ARCHITECTURE ex OF ddf IS BEGIN 【例】D触发器的VHDL语言描述