Synthesis tool Translation Logic optimization Mapping Simulation and Synthesis are components of a design methodology always mumble mumble Synthesis gates,gates,gates, blah blah Synthesizable Verilog Technology Mapping 白白白白白白白白白白 800000000 0中中中中中中中中 0 中中中中中中中中 Place and 00n是09 0 Route clb1 clb2 中中中中中中中单中中 2021/1/13 ASIC Design,by Yan BoASIC Design, by Yan Bo Synthesis tool 2021/1/13 4 Translation + Logic optimization + Mapping