寻址存储器设计:16X8位ROM architecture d of rom is signal id: std logic vector (4 downto 0) begin id < addr ce dataout <=000011ll when id =00000 else "11110000" when id="00010"else "11001100" when id="00100"else 00110011 when id=0o11o else 0101010" when id="01000else w01010101 when id=01o1o else i10011001 when id =01100 elsearchitecture d of rom is signal id: std_logic_vector(4 downto 0); begin id <= addr & ce; dataout <= "00001111" when id ="00000" else "11110000" when id ="00010" else "11001100" when id ="00100" else "00110011" when id ="00110" else "10101010" when id ="01000" else "01010101" when id ="01010" else "10011001" when id ="01100" else 寻址存储器设计： 16x8位ROM