第一章概述 了高速同步8/9预分频器电路。然后采用片上集成的线性稳压器给压控振荡器供 电，设计了多子带压控振荡器以降低其调谐增益。小的调谐增益不但减小了滤波 器面积，而且优化了环路的相位噪声性能。 第四章“芯片设计及测试”给出了芯片照片和测试结果。 第五章“总结与展望”对本文做出了总结，并对今后的工作做了简要的展望。 参考文献 [1]Tom A.D.Riley,Miles A.Copeland,TAD A.Kwasniewski,"Delta-Sigma Modulation in Fractional-N Frequency Synthesis,"IEEE J.Solid-State Circuits,vol.48,no.5,pp. 553-559,May1993. [2]Enrico Temporiti,Guido Albasini,Ivan Bietti,Rinaldo Castello,Matteo Colombo,"A 700-kHz Bandwidth Sigma-Delta Fractional Synthesizer With Spurs Compensation and Linearization Technique for WCDMA Applications,"IEEE J.Solid-State Circuits, vol.39,no.9,pp.1446-1454,Sep.2004. [3]Hamid R.Rategh,et al."A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver,"IEEE J.of Solid-State Circuits,vol.35,no.5,pp.780-787,May 2000. [4]Bram De Muer,Michiel S.J.Steyaert,"On The Analysis of Sigma-Delta Fractional-N Frequency Synthesizers for High-Spectral Purity,"IEEE Transactions on Circuits and System,vol.50,no.11,pp.784-793,Nov.2003. [5]Brownlee,M.Hanumolu,P.K.Mayaram,K.;Un-Ku Moon,"A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning,"IEEE J.Solid-State Circuits vol.41,no.12,pp.2720-2728,Dec.2006. 3第一章    概述 3 了高速同步 8/9 预分频器电路。然后采用片上集成的线性稳压器给压控振荡器供 电，设计了多子带压控振荡器以降低其调谐增益。小的调谐增益不但减小了滤波 器面积，而且优化了环路的相位噪声性能。 第四章“芯片设计及测试”给出了芯片照片和测试结果。 第五章“总结与展望”对本文做出了总结，并对今后的工作做了简要的展望。 参考文献 [1] Tom A. D. Riley, Miles A. Copeland, TAD A. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE J. Solid-State Circuits, vol. 48, no. 5, pp. 553–559, May 1993. [2] Enrico Temporiti, Guido Albasini, Ivan Bietti, Rinaldo Castello, Matteo Colombo, ”A 700-kHz Bandwidth Sigma-Delta Fractional Synthesizer With Spurs Compensation and Linearization Technique for WCDMA Applications,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1446–1454, Sep. 2004. [3] Hamid R. Rategh, et al. “A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver,” IEEE J. of Solid-State Circuits, vol. 35, no. 5, pp. 780–787, May 2000. [4] Bram De Muer, Michiel S. J. Steyaert, “On The Analysis of Sigma-Delta Fractional-N Frequency Synthesizers for High-Spectral Purity,” IEEE Transactions on Circuits and System, vol. 50, no. 11, pp. 784–793, Nov. 2003. [5] Brownlee, M. ; Hanumolu, P.K. ; Mayaram, K. ; Un-Ku Moon，"A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2720–2728, Dec. 2006