peed up paging Effective memory-access time time needed for every data/instruction access TWo time memory-access time; reduces performance by half Access the page table access the data/instruction Solution A special fast-lookup hardware cache called associative registers or translation look-aside buffers (TLBsSpeed up paging • Effective memory-access time, time needed for every data/instruction access – Two time memory-access time; reduces performance by half – Access the page table & Access the data/instruction • Solution: – A special fast-lookup hardware cache called associative registers or translation look-aside buffers (TLBs)