For each circuit in the input, print its case number(starting with 1), followed by a colon and a blank, and then the circuit analysis, which will be one of the following(with replaced by the appropriate gate number) i output inverte Gate is failing; output stuck at 0 Gate is failing output stuck at 1 Unable to totally classify the failure The circuits pictured in Figure I and Figure 2 are used in the first and last sample test cases Sample Input Output for the Sample Input Case 1: No faults detected fy the fai Case 3: Gate l is failing; output stuck at Case 4: Gate l is failing; output inverted Case 5: g failing; output stuck at 0 100 11 1i2 011i 0 3 104 n 4123 3 0 0101 0 11100 00001Output For each circuit in the input, print its case number (starting with 1), followed by a colon and a blank, and then the circuit analysis, which will be one of the following (with # replaced by the appropriate gate number): No faults detected Gate # is failing; output inverted Gate # is failing; output stuck at 0 Gate # is failing; output stuck at 1 Unable to totally classify the failure The circuits pictured in Figure 1 and Figure 2 are used in the first and last sample test cases. Sample Input Output for the Sample Input 2 2 1 o i1 i2 n g1 2 2 1 0 0 0 0 1 2 1 1 a i1 i2 1 1 1 0 1 2 1 1 a i1 i2 1 2 1 0 1 1 1 1 1 1 1 n i1 1 2 1 1 0 0 3 4 4 n g4 a i1 i2 o i2 i3 x i3 i1 2 3 4 1 4 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 Case 1: No faults detected Case 2: Unable to totally classify the failure Case 3: Gate 1 is failing; output stuck at 1 Case 4: Gate 1 is failing; output inverted Case 5: Gate 2 is failing; output stuck at 0