Abstract In wireless communication applications,frequency synthesizer is used to generalize high presise LO signals.In phase locked loop(PLL)-based frequency synthesizers,the frequency divider is one of the most important building blocks.It determines the highest speed and the frequency range of the frequency synthesizer.In multi-standard applications,such as the DTV-Tuner,divider may be used to extend the frequency range of the frequency synthesizer,or to generate the quadrature(1/Q)signal.The main focus of this thesis is the research of the applications of divider in frequency synthesizers,and the silicon verification of a quadrature divider with wide frequency range is realized. Firstly,this thesis summarizes a basic knowledge about frequency synthesizers,then focus on the application of frequency divider in frequency synthesizer.A comprehensive summary and comarisions of several main kinds of dividers are presented,including their structures and operating principles,and both the advantages and disadvantages in performance. Secondly,a detailed analysis of Pulse-Swallow Counter based multi-modulus programmable frequency divider is presented.The thesis presents a new structure of asynchronous 4/4.5 dual-modulus prescaler,the reduced number of transistors results in the reduction of power consumption and the chip area.A new structure of the Swallow Counter is proposed,which works well with the Program Counter which chooses"2"as the end-of-count state,thus the multi-modulus programmable frequency divider can operate at higher speed. Thirdly,a quadrature divider is realized in SMIC 0.18um technology,which can generalize the quadrature signal of 50~860MHz for DTV-Tuners.Through the choice of the divider structure,the number of mixers used in the receiver can be reduced from 5 to 1,which reduces the chip area and the power consumption. Finally,the measurement results are given.The core area of the chip is 390umx350um,and the maximum current of the core circuit is 6mA.The measurement result shows that the divider can operate well,and the performance agrees well with the design requirement.The mismatch of I/Q IVAbstract In wireless communication applications, frequency synthesizer is used to generalize high presise LO signals. In phase locked loop(PLL)-based frequency synthesizers, the frequency divider is one of the most important building blocks. It determines the highest speed and the frequency range of the frequency synthesizer. In multi-standard applications, such as the DTV-Tuner, divider may be used to extend the frequency range of the frequency synthesizer, or to generate the quadrature (I/Q) signal. The main focus of this thesis is the research of the applications of divider in frequency synthesizers, and the silicon verification of a quadrature divider with wide frequency range is realized. Firstly, this thesis summarizes a basic knowledge about frequency synthesizers, then focus on the application of frequency divider in frequency synthesizer. A comprehensive summary and comarisions of several main kinds of dividers are presented, including their structures and operating principles, and both the advantages and disadvantages in performance. Secondly, a detailed analysis of Pulse-Swallow Counter based multi-modulus programmable frequency divider is presented. The thesis presents a new structure of asynchronous 4/4.5 dual-modulus prescaler, the reduced number of transistors results in the reduction of power consumption and the chip area. A new structure of the Swallow Counter is proposed, which works well with the Program Counter which chooses “2” as the end-of-count state, thus the multi-modulus programmable frequency divider can operate at higher speed. Thirdly, a quadrature divider is realized in SMIC 0.18μm technology, which can generalize the quadrature signal of 50~860MHz for DTV-Tuners. Through the choice of the divider structure, the number of mixers used in the receiver can be reduced from 5 to 1, which reduces the chip area and the power consumption. Finally, the measurement results are given. The core area of the chip is 390μm×350μm, and the maximum current of the core circuit is 6mA. The measurement result shows that the divider can operate well, and the performance agrees well with the design requirement. The mismatch of I/Q IV