◎ Example on Msi Write-Back Protocol PrRd/- PrWr/ P us 7 PrWr/Bus rdx bus rd/flush、 PrWr/BusRdX Bus RdX/Flush Replace/ BusWE Memory PrRd/BusRd PrRd/-Replacel- BusRdX— yO devices 7 Processor Action State P1 State p2 State P3 Bus Action Data from 1. 1 reads u Busrd Memory 2 P3 reads u BusRd Memory 3. P3 writes u BusRdX Memory 4. P1 reads u BusRd. flush P3 cache 5. P2 reads u s BusRd Memory 2021/2/1 计算机体系结构Example on MSI Write-Back Protocol 2021/2/1 计算机体系结构 11 Memory I/O devices u: P1 P2 P3 u S 75 u S 7 u MS 57 1. P1 reads u S BusRd Memory 2. P3 reads u S S BusRd Memory 3. P3 writes u I M BusRdX Memory 4. P1 reads u S S BusRd, Flush P3 cache 5. P2 reads u S S S BusRd Memory Processor Action State P1 State P2 State P3 Bus Action Data from 5 7 IS S M I S PrRd/— PrWr/— PrRd/BusRd PrWr/BusRdX PrWr/BusRdX PrRd/— BusRd/— BusRd/Flush BusRdX/Flush Replace/BusWB BusRdX/— Replace/—