intersil CD4518BMS CD4520BMS December 1992 CMOS Dual Up counters Features Pinout High Voltage Ty pes(20V Rating) CD4518BMS, CD4520BMS CD4518BMS Dual BCD Up Counter TOP VIEW CD4520BMS Dual Binary Up Counter Medium Speed Operation 6MHz Typical Clock Frequency at 10V ENABLE A回 15RESETB Positive or Negative Edge Triggering 1A区 14Q4B Synchronous Internal Carry Propagation 13Q3B 100% Tested for Quiescent Current at 20V 12 5v, 10V and 15V Parametric Ratings 田QB Maximum Input Current of 1uA at 18V Over Full Pack RESET A区 回 ENABLE B age Temperature Range; 100nA at 18V and +25C 9CLOCKB Noise Margin(Over Full Package/ Temperature Range) 1V at VDD= 5V 2V at VDD= 10V 2.5V at VDD= 15V Standardized Symmetrical Output Characteristics Meets All Requirements of JEDEC Tentative Standard No. 13B,"Standard Specifications for Description of Functional Diagram 'B Series CMos Devices Applications Multistage Synchronous Counting Q1A CLOCK A ÷10:16 Multistage Ripple Counting Q2A Frequency Dividers Description RESET A CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going Q CLOCK B or negative-going transition. For single unit operation the 10÷1612 ENABLE input is maintained high and the counter advances ENABLE on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines The counter can be cascaded in the ripple mode by connect ing Q4 to the enable input of the subse equent counter while RESETB the CLOCK input of the latter is held low The CD4518BMS and CD4520BMS are supplied in these 16-lead outline packages Braze seal DIP H4S Frit Seal DIP Ceramic Flatpack *H6P tH6W CD4518B Only tCD4520B Only CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures ile Number 3342 1-888-INTERSIL or 321-724-71431 Copyright Intersil Corporation 1999 7-12067-1206 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 December 1992 CD4518BMS, CD4520BMS CMOS Dual Up Counters Features • High Voltage Types (20V Rating) • CD4518BMS Dual BCD Up Counter • CD4520BMS Dual Binary Up Counter • Medium Speed Operation - 6MHz Typical Clock Frequency at 10V • Positive or Negative Edge Triggering • Synchronous Internal Carry Propagation • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Pack￾age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Multistage Synchronous Counting • Multistage Ripple Counting • Frequency Dividers Description CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connect￾ing Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low. The CD4518BMS and CD4520BMS are supplied in these 16-lead outline packages: Braze Seal DIP H4S Frit Seal DIP H1F Ceramic Flatpack *H6P †H6W *CD4518B Only †CD4520B Only File Number 3342 Pinout CD4518BMS, CD4520BMS TOP VIEW Functional Diagram 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 CLOCK A ENABLE A Q1A Q2A Q3A Q4A VSS RESET A VDD Q4B Q3B Q2B Q1B ENABLE B CLOCK B RESET B VSS = 8 VDD = 16 ÷10/÷16 C R 1 4 5 6 Q1A Q2A Q3A Q4A RESET A 7 2 CLOCK A ENABLE A ÷10/÷16 C R 9 12 13 14 Q1B Q2B Q3B Q4B RESET B 15 10 CLOCK B ENABLE B 3 11