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(刘雨辰,王佳,陈云霁,等.计算机系统模拟器研究综述.计算机研究与发展,2015,52(1):3) [24]Gateley J,Blatt M,Chen D,et al.UltraSPARC-I emulation /I Proc of the 32nd ACM/IEEE Design Automation Conf. New York,1995:13 [25]Zhou S,Prasanna VK.Accelerating graph analytics on CPU-FPGA heterogeneous platform.International Symposium on Computer Architecture&High Performance Computing,2017:137 [26]Zhou H W,Xu S,Wang Z Y,et al.FPGA verification for memory link interface of many-core processor.Journal of National University of Defense Technology,2018,40(3):176 (周宏伟,徐实,王忠奕,等.众核处理器访存链路接口的FPGA验证.国防科技大学学报,2018,40(3):176) [27]Pang K,ShiZ F,Zhou J H,et al.Network topology exploration of coarse-grained reconfigurable architecture based on FPGA.Journal of Tianjin University(Science and Technology),2018,51(5):507 (庞科,史再峰,周佳慧,等.基于PGA的粗粒度可重构系统拓扑网络结构开发.天津大学学报(自然科学与工程 技术版),2018,51(⑤):507) [28]Liu Y F,Liu P,Jiang Y T,et al.Building a multi-FPGA-based emulation framewor networks-on-chip design and verification.International Journal of Electronics-INTJ Electron.2010.97(1):124 [29]Hu W,Wang J,Gao X,etal.Godson-3:a scalable multicore RISC processor with x8 em ation.IEEE Micro,2009.29 (2):17 [30]Kalla R,Sinharoy B.Tendler JM.IBM Power5 chip:a dual-core multithreaded pro IEEE Micro,2004,24(2):40 [31]Kongetira P,Aingaran K,Olukotun K.Niagara:a 32-way multithreaded Sparc processor.IEEE Micro,2005,25(2):21 [32]Chen X,Jha NK.A 3-D CPU-FPGA-DRAM hybrid architecture computation.IEEE Transactions on Very Large Scale Integration Systems,2016,24 (5):1649 [33]Wang H D.Gao X,Chen Y J,et al.Interconnection of Go ore processor.Computer Technology and Development,2008,45(12:2001 (王焕东,高翔,陈云霁,等.龙芯3号互联系统的设与实现.计算机研究与发展,2008.45(12):2001) [34]Feng KK,Jia F,Du X J,et al.Design and realization of T interconnection and memory fault diagnosis method for Loongson-3 mainboard.Computer Measurement Control,2020.28(6):1 (冯珂珂,贾凡,杜晓杰,等.龙芯3号板卡HT互联及内存故障诊断方法的设计与实现.计算机测量与控制,2020, 28(6):1) 录用稿件(刘雨辰, 王佳, 陈云霁, 等. 计算机系统模拟器研究综述[J]. 计算机研究与发展, 2015, 52(1): 3) [24] Gateley J, Blatt M, Chen D, et al. UltraSPARC-I emulation // Proc of the 32nd ACM/IEEE Design Automation Conf. New York, 1995: 13 [25] Zhou S, Prasanna VK. Accelerating graph analytics on CPU-FPGA heterogeneous platform. International Symposium on Computer Architecture & High Performance Computing, 2017: 137 [26] Zhou H W, Xu S, Wang Z Y, et al. FPGA verification for memory link interface of many-core processor. Journal of National University of Defense Technology, 2018, 40(3): 176 (周宏伟, 徐实, 王忠奕, 等. 众核处理器访存链路接口的 FPGA 验证. 国防科技大学学报, 2018, 40(3): 176) [27] Pang K, Shi Z F, Zhou J H, et al. Network topology exploration of coarse-grained reconfigurable architecture based on FPGA. Journal of Tianjin University(Science and Technology), 2018, 51(5): 507 (庞科, 史再峰, 周佳慧, 等. 基于 FPGA 的粗粒度可重构系统拓扑网络结构开发. 天津大学学报(自然科学与工程 技术版), 2018, 51(5): 507) [28] Liu Y F,Liu P,Jiang Y T, et al. Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification. International Journal of Electronics-INT J Electron, 2010, 97(10): 1241 [29] Hu W, Wang J, Gao X, et al. Godson-3: a scalable multicore RISC processor with x86 emulation. IEEE Micro, 2009, 29 (2): 17 [30] Kalla R, Sinharoy B, Tendler JM. IBM Power5 chip: a dual-core multithreaded processor. IEEE Micro, 2004, 24(2): 40 [31] Kongetira P, Aingaran K, Olukotun K. Niagara: a 32-way multithreaded Sparc processor. IEEE Micro, 2005, 25(2): 21 [32] Chen X, Jha NK. A 3-D CPU-FPGA-DRAM hybrid architecture for low-power computation. IEEE Transactions on Very Large Scale Integration Systems, 2016, 24 (5): 1649 [33] Wang H D, Gao X, Chen Y J, et al. Interconnection of Godson-3 multi-core processor. Computer Technology and Development, 2008, 45(12): 2001 (王焕东, 高翔, 陈云霁, 等. 龙芯 3 号互联系统的设计与实现. 计算机研究与发展, 2008, 45(12): 2001) [34] Feng K K, Jia F, Du X J, et al. Design and realization of HT interconnection and memory fault diagnosis method for Loongson-3 mainboard. Computer Measurement & Control, 2020, 28(6): 1 (冯珂珂, 贾凡, 杜晓杰, 等. 龙芯 3 号板卡 HT 互联及内存故障诊断方法的设计与实现.计算机测量与控制, 2020, 28(6): 1) 录用稿件,非最终出版稿
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