本课程的主要内容 Simple machine design(Chapter 1, Appendix A, Appendix C) ISAS, Iron Law, simple pipelines Memory hierarchy(Chapter 2, Appendix B) DRAM, caches, virtual memory systems Complex pipelining(Chapter 3) score-boarding, out-of-order issue Explicitly parallel processors(Chapter 4 vector machines, vLlw machines, multithreaded machines Multiprocessor architectures( Chapter 5, Chapter 6) memory models, cache coherence, synchronization 1/30/2021 中国科学技术大学5 本课程的主要内容 • Simple machine design（Chapter 1, Appendix A, Appendix C） – ISAs, Iron Law, simple pipelines • Memory hierarchy (Chapter 2，Appendix B) – DRAM, caches, virtual memory systems • Complex pipelining (Chapter 3) – score-boarding, out-of-order issue • Explicitly parallel processors (Chapter 4) – vector machines, VLIW machines, multithreaded machines • Multiprocessor architectures (Chapter 5, Chapter 6) – memory models, cache coherence, synchronization 1/30/2021 中国科学技术大学