Synchronization 101 Crossing between clock domains is a similar issue to managing asynchronous ce no relationship between the multiple clock domains can assumed, the inputs from Block A to Block B must be assumed to be asynchro nous inputs. The traditional way of synchronizing an asynchronous input signal is shown in Figure 5 nput from Output to Block b' s Clock B FIGURE 5. Synchronizing an Asynchronous Input Two D-type flip-flops are used; two synchronization stages are usually sufficient. Only the rarest applications might demand three stages of synchronization. If your silicon library supports metastable-hardened flip-flops, then the first stage hould use such a device. Typically, metastable-hardened flip-flops guarantee at their Q outputs will settle after a given maximum time, no matter how close the data transition is to the flip-fiop's clock edge This method of information interchange has one drawback. If the strobe has the form of a pulse, it may not be seen by the destination block if the pulse width is less than the destination block's clock(sampling)frequency. This is not a prob- lem if the two blocks exchange levels instead of pulses; however, this is slow, as typically four level exchanges must occur for a two-way handshake. The toggle method described later is an excellent solution to this problem Single-Point Information Imagine that Block A needs to send two bits of information to Block B We could simply duplicate the circuit in Figure 5, with one synchronization circuit for each bit. There is a serious problem which should be clear: occasionally, the circum- stance will arise when one bit gets through the two-stage synchronization cir- cuit, while the other does not. The result is ambiguous information and errors The solution is shown back in Figure 4-use a single strobe from Block A to Block B, and send the rest of the information separately. The single-point strobe from a to B informs the destination block that the Data A-B is valid; the originat ing block ensures that there is adequate setup time The Ten Commandments of Excellent DesignCrossing Clock Domains 10 The Ten Commandments of Excellent Design Synchronization 101 Crossing between clock domains is a similar issue to managing asynchronous inputs. Since no relationship between the multiple clock domains can be assumed, the inputs from Block A to Block B must be assumed to be asynchro￾nous inputs. The traditional way of synchronizing an asynchronous input signal is shown in Figure 5: FIGURE 5. Synchronizing an Asynchronous Input Two D-type flip-flops are used; two synchronization stages are usually sufficient. Only the rarest applications might demand three stages of synchronization. If your silicon library supports metastable-hardened flip-flops, then the first stage should use such a device. Typically, metastable-hardened flip-flops guarantee that their Q outputs will settle after a given maximum time, no matter how close the data transition is to the flip-flop’s clock edge. This method of information interchange has one drawback. If the strobe has the form of a pulse, it may not be seen by the destination block if the pulse width is less than the destination block’s clock (sampling) frequency. This is not a prob￾lem if the two blocks exchange levels instead of pulses; however, this is slow, as typically four level exchanges must occur for a two-way handshake. The toggle method described later is an excellent solution to this problem. Single-Point Information Imagine that Block A needs to send two bits of information to Block B. We could simply duplicate the circuit in Figure 5, with one synchronization circuit for each bit. There is a serious problem which should be clear: occasionally, the circum￾stance will arise when one bit gets through the two-stage synchronization cir￾cuit, while the other does not. The result is ambiguous information and errors. The solution is shown back in Figure 4—use a single strobe from Block A to Block B, and send the rest of the information separately. The single-point strobe from A to B informs the destination block that the Data A-B is valid; the originat￾ing block ensures that there is adequate setup time. D Clock B Q Input from Output to Block A D Q Block B’s Logic