6.VHDL描述 基本RS触发器 ENTITY rsh Is PORT(r,s: IN bit; q, nq: OUT bit); 端口(输入输出) END sfm 定义 ARCHITECTURE rsff a OF rsff2 IS BEGIN PROCESS(r S VARIABLE State: bit: =0; BEG GIN 不定状态 ASSERT NOT (r=O AND S=0) 的描述 REPORT Both r and s=0' SEVERITY error 逻辑功能 IF r='l'AND S='l THEN state : =state; 的描述 ELSIF r='1' AND S=0 then state: ='1 ELSE state: =0' END IF 状态输出 9<= state nq<=Not( state); END PROCESS END rsff a;ARCHITECTURE rsff_a OF rsff2 IS BEGIN PROCESS(r, s) VARIABLE state : bit :='0'; BEGIN END PROCESS ; END rsff_a; 6. VHDL描述 一、基本RS触发器 不定状态 的描述 逻辑功能 的描述 状态输出 ENTITY rsff2 IS PORT(r, s : IN bit; q, nq : OUT bit); END rsff2; ASSERT NOT (r='0' AND s ='0') REPORT "Both r and s ='0'" SEVERITY error; IF r='1'AND s='1' THEN state := state; ELSIF r = '1' AND s = '0' THEN state := '1'; ELSE state := '0'; END IF; q <= state ; nq <= NOT ( state ) ; 端口(输入/输出） 定义