MULTIPLIER ut 女 800K “式“ 7 M10 vCO FIGURE 13. 7 Phase-locked loop circuit for transient analysis, created with PSPICE. sources or asymmetries exist that would start a real oscillator--it must be done manually. The capacitor CI would have to be placed off-chip, and bond pad capacitance(CPADI and CPAD2)have been included at the capacitor nodes. Including the pad capacitances is very important if a small capacitor Cl is used for high frequency operation In this example, the Pll is to be used as a FM detector circuit and the FM signal is applied to the input using a single frequency FM voltage source. The carrier frequency is 600 kHz and the modulation frequency is 60 kHz. Figure 13.8 shows the input voltage and the output voltage of the PlL at the vCo output and at the phase detector output. It can be seen that after a brief starting transient, the PLL locks onto the input signal Loop Filter output 3.0vr 工 nput signa 中与1 FIGURE 13.8 Transient analysis results of PLL circuit, created using PSPICE c 2000 by CRC Press LLC© 2000 by CRC Press LLC sources or asymmetries exist that would start a real oscillator—it must be done manually. The capacitor C1 would have to be placed off-chip, and bond pad capacitance (CPAD1 and CPAD2) have been included at the capacitor nodes. Including the pad capacitances is very important if a small capacitor C1 is used for high￾frequency operation. In this example, the PLL is to be used as a FM detector circuit and the FM signal is applied to the input using a single frequency FM voltage source. The carrier frequency is 600 kHz and the modulation frequency is 60 kHz. Figure 13.8 shows the input voltage and the output voltage of the PLL at the VCO output and at the phase detector output. It can be seen that after a brief starting transient, the PLL locks onto the input signal FIGURE 13.7 Phase-locked loop circuit for transient analysis, created with PSPICE. FIGURE 13.8 Transient analysis results of PLL circuit, created using PSPICE