3-Way Pipelined Version Figure 4.33 A)P310 100ps 20 ps 100ps 20 ps 100ps 20 ps Comb Comb R Comb R logic e logic Delay 360 ps gIc e A g B C Throughput =8.33 GOP g g Clock System a Divide com binational logic into 3 blocks of 100 ps each a Can begin new operation as soon as previous one passes through stage A e Begin new operation every 120 ps Overall latency increases o 360 ps from start to finish -9 Processor– 9 – Processor 3-Way Pipelined Version System ◼ Divide combinational logic into 3 blocks of 100 ps each ◼ Can begin new operation as soon as previous one passes through stage A. ⚫ Begin new operation every 120 ps ◼ Overall latency increases ⚫ 360 ps from start to finish R e g Clock Comb. logic A R e g Comb. logic B R e g Comb. logic C 100 ps 20 ps 100 ps 20 ps 100 ps 20 ps Delay = 360 ps Throughput = 8.33 GOPS Figure 4.33 A) P310