Instruction Decoding Optional Optional 50rAIrB D icode ifun TA B valc Instruction Format ■ nstruction byte icode: ifun a Optional register byte rA: rB a Optional constant word valC 8 Processor– 8 – Processor Instruction Decoding Instruction Format ◼ Instruction byte icode:ifun ◼ Optional register byte rA:rB ◼ Optional constant word valC 5 0 rA rB D icode ifun rA rB valC Optional Optional