Table of Contents 1394 Open Host Controller Interface Specification Release 1.1 Printed 1/10/00 12.3 Physical Responses..... 152 12.4 Physical Response Retries...... .152 12.5 Interrupt Considerations for Physical Requests 152 12.6 Bus Reset. 152 13.Host Bus Errors...... 153 13.1 Causes of Host Bus Errors....... .153 13.2 Host Controller Actions When Host Bus Error Occurs 153 13.2.1 Descriptor Read Error 153 13.2.2 xferStatus Write Error. 153 13.2.3 Transmit Data Read Error.................. .154 13.2.4 Isochronous Transmit Data Write Error................ .154 13.2.5 Asynchronous Receive DMA Data Write Error... 154 13.2.6 Isochronous Receive Data Write Error.................... 154 13.2.7physical Read Error.155 13.2.8 Physical Posted Write Error.... 155 13.2.8.1 PostedWriteAddress Register(optional) .156 13.2.8.2 Queue Rules. 157 Annex A.PCI Interface (optional)........... 159 A.1 PCI Configuration Space............ 159 A.2 Busmastering Requirements......... ,159 A.3 PCI Configuration Space for 1394 Open HCI With PCI Interface.... .159 A.3.1 COMMAND Register 160 A.32STATUS Register.........................161 A.3.3 CLASS CODE Register .161 A.3.4 Revision ID Register..... .16] A.3.5 Base Adr o Register............... .161 A.3.6 CAP PTR Register.... 162 A.3.7 PCI_HCI_Control Register 163 A.3.8 PCI Power Management Register Interface........... .163 A.3.8.1 Capability ID Register .163 A.3.8.2 Next Item Pointer Register(Nxt_Ptr)....... ,163 A.3.8.3 Power Management Capabilities Register(PMC) .164 A.3.8.4 Power Management Control/Status(PMCSR)....... ,165 A.3.8.5 PMCSR BSE.................. ,165 A.3.8.6 PM DATA... 165 A.4 PCI Power Management Behavior 166 A.4.1 Power State Transitions. 166 A.4.2 Power State Definitions. 167 A.4.3 PCI PME#Signal................. 168 A.5 PCI Expansion ROM for 1394 Open HCI........... .169 A.6 PCIBus Errors. ...169 Annex B.Summary of Register Reset Values (Informative)........... . ,171 Annex C.Summary of Bus Reset Behavior(Informative) 177 C.10 verview… .177 C.2 Asynchronous Transmit:Request Response .177 C.3 Asynchronous Receive:Request Response. .177 C.4 Isochronous Transmit .177 Page x Copyright 1996-2000 All rights reserved.Page x Copyright © 1996-2000 All rights reserved. Table of Contents 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 12.3 Physical Responses.........................................................................................................................................152 12.4 Physical Response Retries ..............................................................................................................................152 12.5 Interrupt Considerations for Physical Requests ..............................................................................................152 12.6 Bus Reset........................................................................................................................................................152 13. Host Bus Errors............................................................................................................................................................153 13.1 Causes of Host Bus Errors ..............................................................................................................................153 13.2 Host Controller Actions When Host Bus Error Occurs...................................................................................153 13.2.1 Descriptor Read Error ..........................................................................................................................153 13.2.2 xferStatus Write Error..........................................................................................................................153 13.2.3 Transmit Data Read Error ....................................................................................................................154 13.2.4 Isochronous Transmit Data Write Error ...............................................................................................154 13.2.5 Asynchronous Receive DMA Data Write Error ...................................................................................154 13.2.6 Isochronous Receive Data Write Error.................................................................................................154 13.2.7 Physical Read Error .............................................................................................................................155 13.2.8 Physical Posted Write Error .................................................................................................................155 13.2.8.1 PostedWriteAddress Register (optional) ...................................................................................156 13.2.8.2 Queue Rules ..............................................................................................................................157 Annex A. PCI Interface (optional) .....................................................................................................................................159 A.1 PCI Configuration Space .................................................................................................................................159 A.2 Busmastering Requirements ............................................................................................................................159 A.3 PCI Configuration Space for 1394 Open HCI With PCI Interface ...................................................................159 A.3.1 COMMAND Register ...........................................................................................................................160 A.3.2 STATUS Register ..................................................................................................................................161 A.3.3 CLASS_CODE Register .......................................................................................................................161 A.3.4 Revision_ID Register ............................................................................................................................161 A.3.5 Base_Adr_0 Register ............................................................................................................................161 A.3.6 CAP_PTR Register ...............................................................................................................................162 A.3.7 PCI_HCI_Control Register ...................................................................................................................163 A.3.8 PCI Power Management Register Interface...........................................................................................163 A.3.8.1 Capability ID Register ................................................................................................................163 A.3.8.2 Next Item Pointer Register (Nxt_Ptr) .........................................................................................163 A.3.8.3 Power Management Capabilities Register (PMC) ......................................................................164 A.3.8.4 Power Management Control/Status (PMCSR)............................................................................165 A.3.8.5 PMCSR_BSE .............................................................................................................................165 A.3.8.6 PM_DATA ..................................................................................................................................165 A.4 PCI Power Management Behavior ...................................................................................................................166 A.4.1 Power State Transitions.........................................................................................................................166 A.4.2 Power State Definitions.........................................................................................................................167 A.4.3 PCI PME# Signal ..................................................................................................................................168 A.5 PCI Expansion ROM for 1394 Open HCI........................................................................................................169 A.6 PCI Bus Errors.................................................................................................................................................169 Annex B. Summary of Register Reset Values (Informative) ..............................................................................................171 Annex C. Summary of Bus Reset Behavior (Informative) .................................................................................................177 C.1 Overview..........................................................................................................................................................177 C.2 Asynchronous Transmit: Request & Response ................................................................................................177 C.3 Asynchronous Receive: Request & Response ..................................................................................................177 C.4 Isochronous Transmit.......................................................................................................................................177