Chapter 2 Organization of Computers 2.1.1 System Buses The control bus is different from the other two buses. The address bus consists of n lines. which combine to transmit one n-bit address value. Similarly the lines of the data bus work together to transmit a single multibit value. In contrast, the control bus is a collection of individual control signals. These signals indicate whether data is to be read into or written out of the CPu. whether the CPU is accessing memory or an lo device, and whether the l/o device or memory is ready to transfer data. Although this bus is shown as bidirectional in Figure 2-1, it is really a collection of(mostly)unidirectional signals. Most of these signals are output from the cpu to the memory and yo subsystems, although a few are output by these subsystems to the CPU. We examine these signals in more detail when we look at the instruction cycle and the subsystem interface 控制总线与以上两种总线都不相同。地址总线由n根线构成,n根线联合传送一个n位 的地址值。类似地,数据总线的各条线合起来传输一个单独的多位值。相反,控制 总线是单根控制信号的集合。这些信号用来指示数据是要读入CPU还是要从CPU写 出,CPU是要访问存储器还是要访问O设备,是ⅣO设备还是存储器已就绪要传送 数据等等。虽然图21所示的控制总线看起来是双向的,但它实际上(主要)是单向 (大多数都是)信号的集合。大多数信号是从CPU输出到存储器与ⅣO子系统的,只 有少数是从这些子系统输出到CPU的。在介绍指令周期和子系统接口时,我们将详 细地讨论这些信号第和专出语 2-10Chapter 2 Organization of Computers 计算机专业英语 2-10 The control bus is different from the other two buses. The address bus consists of n lines, which combine to transmit one n-bit address value. Similarly, the lines of the data bus work together to transmit a single multibit value. In contrast, the control bus is a collection of individual control signals. These signals indicate whether data is to be read into or written out of the CPU, whether the CPU is accessing memory or an I/O device, and whether the I/O device or memory is ready to transfer data. Although this bus is shown as bidirectional in Figure 2-1, it is really a collection of (mostly) unidirectional signals. Most of these signals are output from the CPU to the memory and I/O subsystems, although a few are output by these subsystems to the CPU. We examine these signals in more detail when we look at the instruction cycle and the subsystem interface. 控制总线与以上两种总线都不相同。地址总线由n根线构成，n根线联合传送一个n位 的地址值。类似地，数据总线的各条线合起来传输一个单独的多位值。相反，控制 总线是单根控制信号的集合。这些信号用来指示数据是要读入CPU还是要从CPU写 出，CPU是要访问存储器还是要访问I/O设备，是I/O设备还是存储器已就绪要传送 数据等等。虽然图2-1所示的控制总线看起来是双向的，但它实际上（主要）是单向 （大多数都是）信号的集合。大多数信号是从CPU输出到存储器与I/O子系统的，只 有少数是从这些子系统输出到CPU的。在介绍指令周期和子系统接口时，我们将详 细地讨论这些信号。 2.1.1 System Buses