CPUS:LATENCY ORIENTED DESIGN Powerful ALU ALU ALU Reduced operation latency Control ALU ALU Large caches CPU Convert long latency memory Cache accesses to short latency cache accesses Sophisticated control DRAM Branch prediction for reduced branch latency Data forwarding for reduced data latency 电子料皮女学 Universityof Electrei Science and TachnolofChina OCPUS: LATENCY ORIENTED DESIGN ▪ Powerful ALU ▪ Reduced operation latency ▪ Large caches ▪ Convert long latency memory accesses to short latency cache accesses ▪ Sophisticated control ▪ Branch prediction for reduced branch latency ▪ Data forwarding for reduced data latency Cache ALU Control ALU ALU ALU DRAM CPU