参考源程序 数据选择器参考程序: LIBRARY IEEE USE IEEE STD LOGIC 1164.ALL: USE IEEE STD LOGIC UNSIGNEDALL. ENTITY a2 IS PORT(A: IN STD LOGIC, B: IN STD LOGIC CON: IN BIT: C: OUT STD LOGIC ) END a2 ARCHITECTURE A OF a2 IS BEGIN C<=A WHEN CON=O ELSE B WHEN CON=T' ELSE END A. 带使能端的计数器参考程序 LIBRARY IEEE. USE IEEE STD LOGIC 1164.ALL USE IEEE STD LOGIC UNSIGNED.ALL. ENTITY CNT4B IS PORT(CLK: IN STD LOGIC, ENA: IN STD LOGIC OUTY: OUT STD LOGIC VECTOR(3 DOWNTO 0)); END CNT4B ARCHiTECtURE behay OF CNT4B IS SIGNAL CQI: STD LOGIC VECTOR(3 DOWNTO 0) BEGIN PROCESS(CLK, ENA) IF CQI=1111 THEN CQI<=0000" ELSIF CLK'EVENT AND CLK='1'THEN IF ENA='I' THEN COI END IF OUTY<= CQI END PROCESS end behav参考源程序： 数据选择器参考程序: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY a2 IS PORT(A:IN STD_LOGIC; B:IN STD_LOGIC; CON:IN BIT; C:OUT STD_LOGIC ); END a2; ARCHITECTURE A OF a2 IS BEGIN C<=A WHEN CON='0' ELSE B WHEN CON='1' ELSE 'Z'; END A; 带使能端的计数器参考程序： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT4B IS PORT (CLK : IN STD_LOGIC; ENA : IN STD_LOGIC; OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END CNT4B; ARCHITECTURE behav OF CNT4B IS SIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK,ENA) BEGIN IF CQI="1111" THEN CQI <= "0000"; ELSIF CLK'EVENT AND CLK = '1' THEN IF ENA = '1' THEN CQI <= CQI + 1; END IF; END IF; OUTY <= CQI ; END PROCESS; END behav;