Typical Performance Characteristics (Continued) Gain and Linearity Error /rite Pulse width Variation Vs Supply Voltage Data hold time +0.D25 INEARITY ERROR 4△ GAIN ERROR 3王减 100 12V,15V -0.125 =25°c 下: 6585105125 55-35-15525456585105125 VEc- SUPPLY VDLTAGE (VD TA AMBIENT TEMPERATURE TA AMBIENT TEMPERATURE (CI DACo830 Series Application Hints These DAC's are the industry's first microprocessor compat- The timing requirements and logic level convention of the ible, double-buffered 8-bit multiplying D to A converters register control signals have been designed to minimize or Double-buffering allows the utmost application flexibility from eliminate external interfacing logic when applied to most a digital control point of view. This 20-pin device is also pin popular microprocessors and development systems. It is for pin compatible(with one exception)with the DAC 1230, a think of thes 12-bit MICRO-DAC. In the event that a systems analog memory locations that provide an analog output quantity. All puts to these DAC's meet TTL voltage level specs and can ng the DAC 1230 can be easily accomplished. By also be driven directly with high voltage CMOs logic in ddress bit Ao to the ILE pin, a two-byte uP write inst non-microprocessor based systems. To prevent damage (double precision) which automatically increments the chip from static discharge, all unused digital inputs dress for the second byte write(starting with Ao=1) can be should be tied to Vcc or ground. If any of the digital inputs used. This allows either an 8-bit or the 12-bit part to be used are inadvertantly left floating the DAC interprets the pin as a with no hardware or software changes. For the sin ogc“1 pplication, this pin should be tied to Vcc(also see other uses in section 1.1) 1.1 Double-Buffered o Analog signal control versatility is provided by a precision Updating the analog output of these DAC's in a R-2R ladder network which allows full 4-quadrant multiplica double-buffered manner is basically a two step or double tion of a wide range bipolar reference voltage by an applied write operation. In a microprocessor system two unique digital word. system addresses must be decoded, one for the input latch controlled by the Cs pin and a second for the DAC latch 1.0 DIGITAL CONSIDERATIONS which is controlled by the XFER line. If more than one DAC A most unique characteristic of these DAC's is that the 8-bi is being driven, Figure 2, the CS line of each DAC would digital input byte is double-buffered. This means that the typically be decoded individually, but all of the converters data must transfer through two independently controlled 8-bit ould share a common xFer address to allow simultaneous latching registers before being applied to the R-2R ladder network to change the analog output. The addition of a tion is shown, Figure Of DAC's. The timing for this opera- second register allows two useful control features. First, any It is important to note that the analog outputs that will change DAC in a system can simultaneously hold the current DAC after a simultaneous transfer are those from the dAcs data in one register(DAC register) and the next data word in whose input register had been modified prior to the the second register (input register) to allow fast updating of command the DAC output on demand. Second, and probably more system to be updated to their new analog output levels simultaneously via a common strobe signal ww.national. comTypical Performance Characteristics (Continued) Gain and Linearity Error Variation vs. Supply Voltage Write Pulse Width Data Hold Time 00560829 00560830 00560831 DAC0830 Series Application Hints These DAC’s are the industry’s first microprocessor compat￾ible, double-buffered 8-bit multiplying D to A converters. Double-buffering allows the utmost application flexibility from a digital control point of view. This 20-pin device is also pin for pin compatible (with one exception) with the DAC1230, a 12-bit MICRO-DAC. In the event that a system’s analog output resolution and accuracy must be upgraded, substitut￾ing the DAC1230 can be easily accomplished. By tying address bit A0 to the ILE pin, a two-byte µP write instruction (double precision) which automatically increments the ad￾dress for the second byte write (starting with A0=“1”) can be used. This allows either an 8-bit or the 12-bit part to be used with no hardware or software changes. For the simplest 8-bit application, this pin should be tied to VCC (also see other uses in section 1.1). Analog signal control versatility is provided by a precision R-2R ladder network which allows full 4-quadrant multiplica￾tion of a wide range bipolar reference voltage by an applied digital word. 1.0 DIGITAL CONSIDERATIONS A most unique characteristic of these DAC’s is that the 8-bit digital input byte is double-buffered. This means that the data must transfer through two independently controlled 8-bit latching registers before being applied to the R-2R ladder network to change the analog output. The addition of a second register allows two useful control features. First, any DAC in a system can simultaneously hold the current DAC data in one register (DAC register) and the next data word in the second register (input register) to allow fast updating of the DAC output on demand. Second, and probably more important, double-buffering allows any number of DAC’s in a system to be updated to their new analog output levels simultaneously via a common strobe signal. The timing requirements and logic level convention of the register control signals have been designed to minimize or eliminate external interfacing logic when applied to most popular microprocessors and development systems. It is easy to think of these converters as 8-bit “write-only” memory locations that provide an analog output quantity. All inputs to these DAC’s meet TTL voltage level specs and can also be driven directly with high voltage CMOS logic in non-microprocessor based systems. To prevent damage to the chip from static discharge, all unused digital inputs should be tied to VCC or ground. If any of the digital inputs are inadvertantly left floating, the DAC interprets the pin as a logic “1”. 1.1 Double-Buffered Operation Updating the analog output of these DAC’s in a double-buffered manner is basically a two step or double write operation. In a microprocessor system two unique system addresses must be decoded, one for the input latch controlled by the CS pin and a second for the DAC latch which is controlled by the XFER line. If more than one DAC is being driven, Figure 2, the CS line of each DAC would typically be decoded individually, but all of the converters could share a common XFER address to allow simultaneous updating of any number of DAC’s. The timing for this opera￾tion is shown, Figure 3. It is important to note that the analog outputs that will change after a simultaneous transfer are those from the DAC’s whose input register had been modified prior to the XFER command. DAC0830/DAC0832 9 www.national.com