libraryieee, useleee.s std_ logic_1164. all; use ieeestd_logic_unsigned.all; entity mchange_1 is port(clk, clrin std_logic, m: inintegerrange0 to 99; g: bufferinteger range0 to 99) end mchange_1; architecture one of mchange_l is signal md: integer; egin process(clr, clk, m) egin md<=m-1 if clr=1then q <=“0 elsifclk event and clk=1then if q=md then q<= 0 else q<=q+1 end if; nd if: eny end process; dlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mchange_1 is port(clk, clr:in std_logic; m: in integer range 0 to 99; q: buffer integer range 0 to 99); end mchange_1; architecture one of mchange_1 is signal md: integer; begin process(clr,clk,m) begin md<=m-1; if clr=‘1’ then q<=‘0’; elsif clk’event and clk=‘1’ then if q=md then q<=‘0’; else q<=q+1; end if; end if; end process; end one;