EDA技术讲义 【例】 PORT( zI, 72, 73, 74: out std logic) SIGNAL Value: INTEGER RANGE OTO 15 CasE value is WHEN O value=0 时 WHEN 1 3 Z2<=“0 value=1或3时 WhEN 4TO7 2 73 value=4、5、6、72时 WHEN OTHERS value=8-15时 END CASEEDA技术讲义 PORT(… z1 , z2 , z3 , z4 : out std_logic); … SIGNAL value : INTEGER RANGE 0 TO 15; CASE value IS WHEN 0 => z1 <= ‘1’ ; - - value=0时 WHEN 1 | 3 => z2 <= ‘0’ ; - - value=1或3时 WHEN 4 TO 7 | 2 => z3 <= ‘1’ ; - - value=4、5、6、7或2时 WHEN OTHERS => z4 <= ‘1’ ; - - value=8~15时 END CASE 【例】