9.2以题解答269 ∥调用ader-1bit模块,生成模块m3 m4(A[0],B[0J,CI,C1); ∥调用 Carryl模块,生成模块 m5(A[0],B[0],A[1],B[l,Cl,C2) ∥调用Cary2模块,生成模块m5 arI 3m6(A[0],B0],A[1],B],A[2],B[2],CI,C3); ∥调用Cary3模块,生成模块m6 arty m7(A0],B[0],A[1],B[1],A[2],B[2],A[3],B[3],CI,CO) ∥调用Cary4模块,生成模块m7 d module ∥1位的全加器模块(不计算进位信号) ule adder_l bit(a, b,c input a, b, c tput xor g2 (sum, d, c) endmodule ∥通过A0,B0,C计算C1 module Carry 1(AO, B0, CT, Cl) C assign Cl =((AO&&B0)"((ao -B0)&&CI) endmodule ∥通过A0,B0,A1,B1和CI计算C2 module Carry2( A0, BO, Al, BI, CI, C2) input AO, B0, Al, BI, Cl tput wire Cltemp; Carry I foreI(AO, B0, CI, CI temp) assign C2=(Al&&B1)-((AlB1)&&Cltemp) endimodu