先看一个VHDL代码的例子 1. VHDL code position: p77 ex4 7 DFF1 Page: 77 LIBARY IEEE. USE IEEE STD LOGIC 1164.ALL: Example: 4-7 ENTITY DFF1 IS PORT CLK STD LOGIC D触发器 7 STD LOGIC OUT STD LOGIC 10. END ENTITY DFF1 11. ARCHITECTURE bhV OF DFF1 IS 12. SIGNAL Q1 STD LOGIC UIA 13. BEGIN PROCESS( CLK PRE BEGIN IF CLK'EVENT AND CLK=1 THEN 432 - why CLK 6 END F D Q<=Q1; C CLR END PROCESS END ARCHITECTURE bhv. SN74HC74先看一个VHDL代码的例子 1. VHDL code position: p77_ex4_7_DFF1 2. ------------------------------------------------------------------------------- 3. LIBARY IEEE; 4. USE IEEE.STD_LOGIC_1164.ALL; 5. ENTITY DFF1 IS 6. PORT ( CLK : IN STD_LOGIC; 7. D : IN STD_LOGIC; 8. Q : OUT STD_LOGIC 9. ); 10. END ENTITY DFF1; 11. ARCHITECTURE bhv OF DFF1 IS 12. SIGNAL Q1 : STD_LOGIC; 13. BEGIN 14. PROCESS ( CLK ) 15. BEGIN 16. IF CLK'EVENT AND CLK = '1' THEN 17. Q1 <= D; -- why don't use "Q <=D" ?? 18. END IF; 19. Q<=Q1; 20. END PROCESS; 21. END ARCHITECTURE bhv; Page:77 Example: 4-7 D触发器