Cache对系统性能的影响 -240 cycles Main Memory Core 0 Core 2 MC 10s L3B 8 System Bus -14 cycles L3 0 Controller MCU GX -3 cycles 1 Controller 2nd Level Cache 1 Level Data Cache MC L3B Core Level Instruction Cache Execution Unit sI cycle -3 cycles MIPS R4000指令流水线 IF IS RF EX DF DS TC WB First-half Second-half First-half Second-half Tag check Instruction memory Reg Data memory RegCache对系统性能的影响 MIPS R4000指令流水线 First-half Second-half First-half Second-half Tag check