16 Chapter 1 Introduction ▣▣▣▣▣▣▣▣▣▣ PLD PLD I PLD PLD ▣口▣口口口口▣口口 ▣▣▣▣▣▣▣▣▣▣ ▣口▣▣口口▣▣▣▣ Programmable Interconnec ▣▣▣▣▣▣▣▣▣▣ ▣口口口口口口口口口 PID PLD PLD PID ▣口口口口口▣▣▣▣ 口口口口口口▣口口口 a ▣=logic block Figure 1-6 Large programmable-logic-device scaling approaches:(a)CPLD:(b)FPGA Proponents of one approach or the other used to get into"religious"argu- ments over which way was better,but the largest manufacturer of large important than chip architecture is that both approaches support a style of design in which products can be moved from design concept to prototype and produc- tion in a very period of time short time Also important in achieving short"time-to-market"for all kinds of PLD. based products is the use of HDLs in their design.Languages like ABEL and VHDL,and their accompanying software toos,allow a design to be compiled, synthesized,and downloaded into a PLD,CPLD,or FPGA literally in minutes The power of highly structured,hierarchical languages like VHDL is especially important in helping designers utilize the hundreds of thousands or millions of gates that are provided in the largest CPLDs and FPGAs 1.8 Application-Specific ICs Perhaps the most interesting developments in IC technology for the average digital designer are not the ever-increasing chip sizes,but the ever-increasing opportunities to"design your own chip."Chips designed for a particular,limited semicustom IC fion-pecife IC uring cost of a product by reducing chip count,physical size,and power consumption,and they often provide higher performance. (NRE) The nonrecurring engineering (NRE)cost for designing an ASIC can exceed the cost ofa discrete design by $5,000 to $250,000 or more.NRE charges are paid to the IC manufacturer and others who are responsible for designing the Copyright 1999 by John F.Wakerly Copying Prohibited 16 Chapter 1 Introduction DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited Proponents of one approach or the other used to get into “religious” argu￾ments over which way was better, but the largest manufacturer of large programmable logic devices, Xilinx Corporation, acknowledges that there is a place for both approaches and manufactures both types of devices. What’s more important than chip architecture is that both approaches support a style of design in which products can be moved from design concept to prototype and produc￾tion in a very period of time short time. Also important in achieving short “time-to-market” for all kinds of PLD￾based products is the use of HDLs in their design. Languages like ABEL and VHDL, and their accompanying software tools, allow a design to be compiled, synthesized, and downloaded into a PLD, CPLD, or FPGA literally in minutes. The power of highly structured, hierarchical languages like VHDL is especially important in helping designers utilize the hundreds of thousands or millions of gates that are provided in the largest CPLDs and FPGAs. 1.8 Application-Specific ICs Perhaps the most interesting developments in IC technology for the average digital designer are not the ever-increasing chip sizes, but the ever-increasing opportunities to “design your own chip.” Chips designed for a particular, limited product or application are called semicustom ICs or application-specific ICs (ASICs). ASICs generally reduce the total component and manufacturing cost of a product by reducing chip count, physical size, and power consumption, and they often provide higher performance. The nonrecurring engineering (NRE) cost for designing an ASIC can exceed the cost of a discrete design by $5,000 to $250,000 or more. NRE charges are paid to the IC manufacturer and others who are responsible for designing the PLD PLD PLD PLD PLD PLD PLD PLD Programmable Interconnect (a) (b) = logic block Figure 1-6 Large programmable-logic-device scaling approaches: (a) CPLD; (b) FPGA. semicustom IC application-specific IC (ASIC) nonrecurring engineering (NRE) cost