多内核DSP ●分组FIE结构 Block diagram: TMS320C6201 VLⅠW指令结构 Program RAM/Cache Data RAM 32-Bit Address 32-Bif Address ●EMIF接口 256-Bit Data 8,16-,32 Bit Data EMIF 512K Bits RAN 512K Bits RAM Host Port 以 Buses 32 C6200 CPU Core Enhanced buffered Program Fetch (1/E1 Instruction Decode Serial Port Enhanced Buffered Emulation (T1/E1) 图M Serial Port N Timer多内核DSP ⚫ 分组FILE结构 ⚫ VLIW指令结构 ⚫ EMIF接口