仿真测试文件: testbench library ieee; process use ieee std logic 1164. all begin entity fa testbench is xt<=o;yt<=0; zt<=0; wait for 10 ns; end fa testbench: xt<=oyt<=o'; Zt<=l; wait for 10 ns architecture beh of fa testbench is xt<=0; yt<='l; Zt<=0; wait for 10 ns component fa xt<=0;yt=l';zt <=l; wait for 10 ns port(a, b ci: in std logic; xt<=l; yt<=0; Zt<=0; wait for 10 ns s, co: out std logic); xt<=lyt<=0;zt<=l; wait for 10 ns end component xt<=l;yt<=l';zt<=0; wait for 10 ns signal xt, yt, zt, st, cot: std logic; xt<=lyt=l';zt<=l; wait for 10 ns begin Xt<=0;yt=0; zt<=0; wait for 10 ns u1: fa port map(xt, yt, zt, st, cot); end process; end beh:仿真测试文件：testbench library ieee; use ieee.std_logic_1164.all; entity fa_testbench is end fa_testbench; architecture beh of fa_testbench is component fa port (a,b,ci: in std_logic; s,co : out std_logic); end component; signal xt,yt,zt,st,cot:std_logic; begin u1: fa port map (xt,yt,zt,st,cot); process begin xt<='0';yt<='0';zt<='0'; wait for 10 ns; xt<='0';yt<='0';zt<='1'; wait for 10 ns; xt<='0';yt<='1';zt<='0'; wait for 10 ns; xt<='0';yt<='1';zt<='1'; wait for 10 ns; xt<='1';yt<='0';zt<='0'; wait for 10 ns; xt<='1';yt<='0';zt<='1'; wait for 10 ns; xt<='1';yt<='1';zt<='0'; wait for 10 ns; xt<='1';yt<='1';zt<='1'; wait for 10 ns; xt<='0';yt<='0';zt<='0'; wait for 10 ns; end process; end beh;