￡ⅫNX° Writing Efficient Testbenches 15400111111111 16001111111110 16601111111110 17201111111101 17801111111011 If an error is detected, it is displayed at the simulator prompt. Figure 4 shows errors displayed in the MTI transcript window DModelSim SE/EE PLUS 5.4e File Edit Design View Run Macro Options Window Help 步1眙B群「1000系0 SIM 166> restart SIM 167> run 1500 #*x Error: vector mismatch Time: 710ns Iteration: 0 Instance: /testbench #*x Error: vector mismatch #t Time: 1250 ns Iteration 0 Instance. /testbench S|M168 Now. 1,500 ns Delta: 0 sim testbench Figure 4: Simulator-Prompt Error Report Guidelines for This section provides guidelines for writing testbenches. Just as planning a circuit design helps Writing achieve better circuit performance, planning a testbench layout improves simulation verification Testbenches Know the simulator before writing the testbench Although commonly-used simulation tools conform to HDL industry standards, these standards do not address several important simulation-specific issues. Different simulators have different features, capabilities, and performance characteristics, and produce different simulation results Event-based vs cycle-based simulation Simulators use event-based or cycle-based simulation methods. Event-based simulators schedule a simulator event when an input, signal, or gate changes value. In an event-based simulator, a delay value can be associated with gates and nets to achieve optimum timing simulation Cycle-based simulators target synchronous designs. They optimize combinatorial logic and analyze results at clock cycles. This ature makes cycle-based simulators faster and more memory efficient than event based simulators. However, since cycle-based simulators do not allow detailed timing specificity, they are not as accurate. For further information on these differences, see Digital Logic Simulation: Event-Driven, Cycle-Based, and Home-Brewed, available at http://www.ednmag.com/ednmag/reg/1996/070496/14df4.htm Scheduling events Event-based simulator vendors employ different algorithms for scheduling simulation vents. Therefore, events that occur at the same simulation time may be scheduled in a different sequence(with delta delays inserted between each event) depending on the scheduling algorithm used by the simulator. To avoid algorithmic dependencies and assure correct results, an event-driven testbench should specify an explicit stimulus sequence www.xilinx.com XAPP199(v1.0)June11,2001 1-800-255-777814 www.xilinx.com XAPP199 (v1.0) June 11, 2001 1-800-255-7778 Writing Efficient Testbenches R 1540 0111111111 1600 1111111110 1660 1111111110 1720 1111111101 1780 1111111011 If an error is detected, it is displayed at the simulator prompt. Figure 4 shows errors displayed in the MTI transcript window. Guidelines for Writing Testbenches This section provides guidelines for writing testbenches. Just as planning a circuit design helps achieve better circuit performance, planning a testbench layout improves simulation verification results. • Know the simulator before writing the testbench. Although commonly-used simulation tools conform to HDL industry standards, these standards do not address several important simulation-specific issues. Different simulators have different features, capabilities, and performance characteristics, and produce different simulation results. - Event-based vs. cycle-based simulation Simulators use event-based or cycle-based simulation methods. Event-based simulators schedule a simulator event when an input, signal, or gate changes value. In an event-based simulator, a delay value can be associated with gates and nets to achieve optimum timing simulation. Cycle-based simulators target synchronous designs. They optimize combinatorial logic and analyze results at clock cycles. This feature makes cycle-based simulators faster and more memory efficient than event￾based simulators. However, since cycle-based simulators do not allow detailed timing specificity, they are not as accurate. For further information on these differences, see Digital Logic Simulation: Event-Driven, Cycle-Based, and Home-Brewed, available at http://www.ednmag.com/ednmag/reg/1996/070496/14df4.htm. - Scheduling events Event-based simulator vendors employ different algorithms for scheduling simulation events. Therefore, events that occur at the same simulation time may be scheduled in a different sequence (with delta delays inserted between each event) depending on the scheduling algorithm used by the simulator. To avoid algorithmic dependencies and assure correct results, an event-driven testbench should specify an explicit stimulus sequence. Figure 4: Simulator-Prompt Error Report