Interleaved Vector Memory System Cray-1, 16 banks 4 cycle bank busy time 12 cycle latency Bank busy time: Time before bank ready to accept next request if stride =1& consecutive elements inter/ea ved across banks number of banks > bank latency then can sustain 1 element/cycle throughput Base Stride Vector Registers Address Generator 0123456789 ABCDEF Memory Banks 1/272021 中国科学技术大学Interleaved Vector Memory System 1/27/2021 中国科学技术大学 • Cray-1, 16 banks, 4 cycle bank busy time, 12 cycle latency – Bank busy time: Time before bank ready to accept next request – If stride = 1 & consecutive elements interleaved across banks & number of banks >= bank latency, then can sustain 1 element/cycle throughput 0 1 2 3 4 5 6 7 8 9 A B C D E F + Base Stride Vector Registers Memory Banks Address Generator 7