Table 1-1. SPI Registers Name Address Range Size(x16) Description SPICCR 0×0000-7040 SPI Configuration Control Register SPICTL 0×0000-7041 SPl Operation Control Register SPIST 0×0000-7042 SPI Status Register SPIBRR 0x0000-7044 SPI Baud Rate Register SPIEMU 0×0000-7046 1 SPI Emulation Buffer Register SPIRXBUF 0×0000-7047 SPI Serial Input Buffer Register SPITXBUF 0x0000-7048 1 SPI Serial Output Buffer Register SPIDAT 0×000-7049 1 SPI Senal Data Register SPIFFTX 0×0000-704A 1 SPI FIFO Transmit Register SPIFFRX 0×0000-704B 1 SPI FIFO Receive Register SPIFFCT 0×0000-704C 1 SPI FIFO Control Register SPIPR 0×0000-704F 1 SPI Priority Control Register Note: The registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. Using 32-bit accesses pro- duces undefined results