在上述设计中,已对需要的4个元件的实体作出了具体规定, 下一步就可以根据这些规定,分头设计具体器件; 上述电路元件也可以采用进程和赋值语句分别描述如下: use ieee std logic 1164. all use ieee std logic arith. all entity shfmult8 is port( a: in std logic vector(7 downto 0) b: in std logic vector(7 downto 0) clk, ld, clr: in std logic g: out std logic vector( 15 downto O)) end shfmult8 architecture beh of shfmult& is signal si: unsigned( 15 downto 0) signal bi: std logic vector( 7 downto O ignal bs: std logic shfreg16: process(clk, clr) if clrl'then as<=(others=>0) elsif (clk'event and clk-'l)then if ld= then as<=00000000"& unsigned(a); as<=as(14 downto 0)&0;--shift to hign bitu4: adder16 port map (as,qi,si); end process; q<=qi+0; end str; 在上述设计中，已对需要的 4 个元件的实体作出了具体规定， 下一步就可以根据这些规定，分头设计具体器件； 上述电路元件也可以采用进程和赋值语句分别描述如下： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity shfmult8 is port ( a: in std_logic_vector(7 downto 0); b: in std_logic_vector(7 downto 0); clk,ld,clr: in std_logic; q: out std_logic_vector(15 downto 0)); end shfmult8; architecture beh of shfmult8 is signal as: unsigned(15 downto 0); signal si: unsigned(15 downto 0); signal qi: unsigned(15 downto 0); signal bi: std_logic_vector(7 downto 0); signal bs: std_logic; begin shfreg16:process (clk,clr) begin if clr='1' then as<=(others=>'0'); elsif (clk'event and clk='1') then if ld='1' then as<="00000000" & unsigned(a); else as<=as(14 downto 0) & '0'; --shift to hign bit