51基本设计流程 513编译前设置 Settings- CHT10 Category General Device User Libraries[ Current Project) Select the family and device you want to target for compilation. +.Timing Analysis Settings + EDA Tool Settings Family: Cyclone ll Show in 'Available devices' list +Compilation Process Settings Package: TQFP Device& Pin Options E] Analysis Synthesis Settings 144 VHDL Input Target device Verilog HDl Input C Auto device selected by the Fitter Default Parameters Specific device selected in ' Available devices' list Core voltage 1.2 Synthesis Netlist Optimizations C Other: n/a y Show advanced devices Physical Synthesis Optimizations Assembler Available devices Design Assistant ame LEs Memor. Embed. PLL ignalT ap ll Logic Analyzer EP2C5T144C8 460811980826 nnrcT14In 图5-6选择目标器件EP2C5T144c8 K 康芯科技5.1 基本设计流程 KX 图5-6 选择目标器件EP2C5T144C8 康芯科技 5.1.3 编译前设置