library ieee; use ieee std logic_1164.all elsif cp event and cp='1 then use ieee std_logic_unsigned ifj="0′andk= en temp<=0 entity jKis qn-temp<=‘1 port(, k,r, s, cp: in std logic; elsifj=‘1andk=“0’tho en g, qn: out std_logic) q-temp<=‘1 djK; qn-temp<= 0 architecture one ofJKis elsifj=1 and k= 1then signal g-temp, qn_temp: stdlogic g_temp<-=not -temp; gin qn_temp<=not qn_temp; process〔, s,j, k, cp) end if be‘0ands=‘1then end if: nd process; q-temp< 0 qs=q-temp elsifr=1 ands=0 then qn<=gn_temp; g-_temp<= 1; end one; qr elsifr='0 temps=q-temp; p<=qn__temp;library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all ; entity JK is port(j,k,r,s,cp:in std_logic ; q, qn:out std_logic); end JK; architecture one of JK is signal q_temp, qn_temp: std_logic ; begin process(r,s,j,k,cp) begin if r=‘0’ and s=‘1’ then q_temp<=‘0’; qn_temp<=‘1’; elsif r=‘1’ and s=‘0’ then q_temp<=‘1’; qn_temp<=‘0’; elsif r=‘0’ and s=‘0’ then q_temp<=q_temp; qn_temp<=qn_temp; elsif cp’event and cp=‘1’ then if j=‘0’ and k=‘1’ then q_temp<=‘0’; qn_temp<=‘1’; elsif j=‘1’ and k=‘0’ then q_temp<=‘1’; qn_temp<=‘0’; elsif j=‘1’ and k=‘1’ then q_temp<=not q_temp; qn_temp<=not qn_temp; end if; end if; end process; q<=q_temp; qn<=qn_temp; end one;