Type Data VHDL is a very rigid type data oriented language Q: What is it means? A: Different type can not do ar iny assignment e. g. a: in belongs to TYPE A b: out belongs to TYPE B b<= a ERROR because a and b is belonging to different types Q: Why vhdl does not allow this? A: This is a kind of protection so engineer will not do different TYpe assignment by mistakeType Data „ VHDL is a very rigid Type Data Oriented Language Q : What is it means? A : Different type can not do any assignment e.g. a : in belongs to TYPE A b : out belongs to TYPE B b <= a; ----- ERROR because a and b is belonging to different types Q : Why VHDL does not allow this ? A : This is a kind of protection, so engineer will not do different TYPE assignment by mistake