0 1c1 c 10l|1110)00{1 [esIs e> Minimal Test Set T: I(01),(10).(11)I FIGURE 85.4 Test set example the occurrence of the single stuck-at faults of either line 1 stuck-at 0(1/0)or of line 2 stuck-at 1(2/1),are Bridging faults occur when two or more lines are shorted together. There are two main nalysis of bridging faults: (1)the theoretical number of possible such faults is extremely operational effect is of a wired logic AND or OR, depending on technology, and it can ever effects in complex CMOS gates CMOS stuck-open faults have been examined recently, as they cannot be modeled from the more classical fault models and are restricted to the CMOS technology. They occur when the path through one of the p-channel or one of the n-channel transistors becomes an open circuit. The main difficulty in detecting this type of fault is that it changes the combinational behavior of a cell into a sequential one. Thus the logical effect is to retain, on a given line, the previous value, introducing a memory state. To detect such a fault, one must apply two stimuli: the first to set a line at a certain value and the second to try and change that value. This, of course, ncreases the complexity of fault detection. Test Pattern generation Test pattern generation is the process of generating a(minimal) set of input patterns to stimulate the inputs of a circuit such that detectable faults can be exercised (if present)[Abramovici et al., 1992]. The process can be divided in two distinct phases: (1)derivation of a test and(2)application of a test. For(1), one must first select appropriate models for the circuit(gate or transistor level)and for faults; one must construct the test such that the output signal from a faulty circuit is different from that of a good circuit. This can be computa- tionally very expensive, but one must remember that the process is done only once at the end of the design age. The generation of a test set can be obtained either by manual methods, by algorithmic methods(with or without heuristics), or by pseudo-random methods On the other hand, for(2), a test is subsequently applied many times to each IC and thus must be efficient both in space(storage requirements for the patterns)and time. Often such a set is not minimal, as near minimality may be sufficient. The main considerations in evaluating a test set are the time to construct a minimal test set; the size of the test pattern generator, le,the load the test patterns; and the equipment required (if external)or the BISt overhead. Most algorithmic test pattern generators are based on the concept of sensitized paths. Given a line in a circuit, one wants to find a sensitized path to take a possible error all the way to an observable output. For example, to sensitize a path that goes through one input of an AND gate, one must set all other inputs of the gate to logic I to permit the sensitized signal to carry through. Figure 85. 4 summarizes the underlying principles of trying to construct a test set. Each column shows the expected output for each input combination of a NAnD gate. Columns 3 to 8 show the output under the presence of a stuck-at fault as per label. The output bits that permit detection of the corresponding fault are shown in a square, and thus at the bottom the minimal test set is listed, comprising the minimal number of distinct patterns necessary to detect all single stuck-at faults e 2000 by CRC Press LLC© 2000 by CRC Press LLC the occurrence of the single stuck-at faults of either line 1 stuck-at 0 (1/0) or of line 2 stuck-at 1 (2/1), are shown as F*. Bridging faults occur when two or more lines are shorted together. There are two main problems in the analysis of bridging faults: (1) the theoretical number of possible such faults is extremely high and (2) the operational effect is of a wired logic AND or OR, depending on technology, and it can even have different effects in complex CMOS gates. CMOS stuck-open faults have been examined recently, as they cannot be modeled from the more classical fault models and are restricted to the CMOS technology. They occur when the path through one of the p-channel or one of the n-channel transistors becomes an open circuit. The main difficulty in detecting this type of fault is that it changes the combinational behavior of a cell into a sequential one. Thus the logical effect is to retain, on a given line, the previous value, introducing a memory state. To detect such a fault, one must apply two stimuli: the first to set a line at a certain value and the second to try and change that value. This, of course, increases the complexity of fault detection. Test Pattern Generation Test pattern generation is the process of generating a (minimal) set of input patterns to stimulate the inputs of a circuit such that detectable faults can be exercised (if present) [Abramovici et al., 1992]. The process can be divided in two distinct phases: (1) derivation of a test and (2) application of a test. For (1), one must first select appropriate models for the circuit (gate or transistor level) and for faults; one must construct the test such that the output signal from a faulty circuit is different from that of a good circuit. This can be computa￾tionally very expensive, but one must remember that the process is done only once at the end of the design stage. The generation of a test set can be obtained either by manual methods, by algorithmic methods (with or without heuristics), or by pseudo-random methods. On the other hand, for (2), a test is subsequently applied many times to each IC and thus must be efficient both in space (storage requirements for the patterns) and in time. Often such a set is not minimal, as near minimality may be sufficient. The main considerations in evaluating a test set are the time to construct a minimal test set; the size of the test pattern generator, i.e., the software or hardware module used to stimulate the circuit under test; the size of the test set itself; the time to load the test patterns; and the equipment required (if external) or the BIST overhead. Most algorithmic test pattern generators are based on the concept of sensitized paths. Given a line in a circuit, one wants to find a sensitized path to take a possible error all the way to an observable output. For example, to sensitize a path that goes through one input of an AND gate, one must set all other inputs of the gate to logic 1 to permit the sensitized signal to carry through. Figure 85.4 summarizes the underlying principles of trying to construct a test set. Each column shows the expected output for each input combination of a NAND gate. Columns 3 to 8 show the output under the presence of a stuck-at fault as per label. The output bits that permit detection of the corresponding fault are shown in a square, and thus at the bottom the minimal test set is listed, comprising the minimal number of distinct patterns necessary to detect all single stuck-at faults. FIGURE 85.4 Test set example