Figure 5. 104(page 302) QA QB Qc QD Positive edge triggered SO CLR a Two serial input: s0, S1 CLK S1 CLR can clear the data freely SR A B C D SL Combined with clock pulse D SOS1=11. load the external data D SOS1=10, shift right, (QA QBQCQDn+l=(SRQA QBQcn 口S0S1=10, shift left (QA QBQCQDn+l=(QBQCQDSL 口5S1=00. inhibit◼ Figure 5.104 (page 302) ◼ Positive edge triggered ◼ Two serial input: S0, S1 ◼ CLR can clear the data freely ◼ Combined with clock pulse  S0S1=11, load the external data  S0S1=10, shift right, ◼ (QAQBQCQD) n+1=(SRQAQBQC ) n  S0S1=10, shift left, ◼ (QAQBQCQD) n+1=(QBQCQDSL)n  S0S1=00, inhibit SR A B C D SL CLK QA QB QC QD CLR S0 S1