Detecting Mispredicted Branch valA dstM ALU Figure 4.64 P347 Condition Trigger Mispredicted Branch E icode =lJXX& le Bch -9 Processor– 9 – Processor Detecting Mispredicted Branch Condition Trigger Mispredicted Branch E_icode = IJXX & !e_Bch M F D Instruction memory PC increment Register file CC ALU Data memory Select PC rB dstE dstM ALU A ALU B Mem. control Addr srcA srcB read write ALU fun. Fetch Decode Execute Memory Write back data out data in A B M E M_valA W _valE W _valM W _valE M_valA W _valM f_PC Predict PC icode Bch valE valA dstE dstM E icode ifun valC valA valB dstE dstM srcA srcB icode ifun rA valC valP predPC d_srcA d_srcB e_Bch M_Bch Sel+Fwd A Fwd B W icode valE valM dstE dstM m_valM W _valM M_valE e_valE M F D Instruction memory PC increment Register file CC ALU Data memory Select PC rB dstE dstM ALU A ALU B Mem. control Addr srcA srcB read write ALU fun. Fetch Decode Execute Memory Write back data out data in A B M E M_valA W _valE W _valM W _valE M_valA W _valM f_PC Predict PC icode Bch valE valA dstE dstM E icode ifun valC valA valB dstE dstM srcA srcB icode ifun rA valC valP predPC d_srcA d_srcB e_Bch M_Bch Sel+Fwd A Fwd B W icode valE valM dstE dstM m_valM W _valM M_valE e_valE m_valM W _valM M_valE e_valE M F D Instruction memory PC increment Register file CC ALU Data memory Select PC rB dstE dstM ALU A ALU B Mem. control Addr srcA srcB read write ALU fun. Fetch Decode Execute Memory Write back data out data in A B M E M_valA W _valE W _valM W _valE M_valA W _valM f_PC Predict PC icode Bch valE valA dstE dstM E icode ifun valC valA valB dstE dstM srcA srcB icode ifun rA valC valP predPC d_srcA d_srcB e_Bch M_Bch Sel+Fwd A Fwd B W icode valE valM dstE dstM m_valM W _valM M_valE e_valE m_valM W _valM M_valE e_valE M F D Instruction memory PC increment Register file CC ALU Data memory Select PC rB dstE dstM ALU A ALU B Mem. control Addr srcA srcB read write ALU fun. Fetch Decode Execute Memory Write back data out data in A B M E M_valA W _valE W _valM W _valE M_valA W _valM f_PC Predict PC icode Bch valE valA dstE dstM E icode ifun valC valA valB dstE dstM srcA srcB icode ifun rA valC valP predPC d_srcA d_srcB e_Bch M_Bch Sel+Fwd A Fwd B W icode valE valM dstE dstM m_valM W _valM M_valE e_valE m_valM W _valM M_valE e_valE m_valM W _valM M_valE e_valE m_valM W _valM M_valE e_valE Figure 4.64 P347