Elimination Before Elimination After Elimination F=Ga+G'b,G=c+d F=ac+ad+bc'd' w:10,M:2,A:2) (w:15,M:4,A:2) b c a Two-level Tradeoff:more area,less delay 2021/1/13 ASIC Design,by Yan Bo 6ASIC Design, by Yan Bo Elimination 2021/1/13 6 After Elimination F=ac+ad+bc’d’ Before Elimination F=Ga+G’b, G=c+d (w:10,M:2,A:2) (w:15,M:4,A:2) Tradeoff: more area, less delay