85 esting 85.1 Digital IC Testing Micaela serra Taxonomy of Testing. Fault Models. Test Pattern Generation Output Response Analysis Bulent I. Dervisoglu 85.2 Design for Test The Testability Problem. Design for Testability. Future for Design Hewlett-Packard Company for Test 85.1 Digital IC Testing Micaela serra In this section we give an overview of digital testing techniques with appropriate reference to material containing all details of the methodology and algorithms. First, we present a general introduction of terminology and a taxonomy of testing methods. Next, we present a definition of fault models, and finally we discuss the main approaches for test pattern generation and data compaction, respectively Taxonomy of Testing The evaluation of the reliability and quality of a digital IC is commonly called testing, yet it comprises distinct phases that are mostly kept separate both in the research community and in industrial practice 1. Verification is the initial phase in which the first prototype chips are"tested"to ensure that they match their functional specification, that is, to verify the correctness of the design Verification checks that all design rules are adhered to, from layout to electrical parameters; more generally, this type of functional testing checks that the circuit: (a)implements what it is supposed to do and(b)does not do what it is not supposed to do Both conditions are necessary. This type of evaluation is done at the design sta and uses a variety of techniques, induding logic verification with the use of hardware description languages, full functional simulation, and generation of functional test vectors. We do not discuss verification techniques here 2. Testing correctly refers to the phase when one must ensure that only defect-free production chips are ackaged and shipped and detect faults arising from manufacturing and/or wear-out. Testing methods must(a)be fast enough to be applied to large amounts of chips during production,(b) take into consideration whether the industry concerned has access to large expensive external tester machines, and(c)consider whether the implementation of built-in self-test(BIST) proves to be advantageous In BIST, the circuit is designed to include its own self-testing extra circuitry and thus can signal directly, luring testing, its possible failure status. Of course, this involves a certain amount of overhead in area, and trade-offs must be considered. The development of appropriate testing algorithms and their tool support can require a large amount of engineering effort, but one must note that it may need to be done only once per design. The speed of application of the algorithm(applied to many copies of the chips c 2000 by CRC Press LLC© 2000 by CRC Press LLC 85 Testing 85.1 Digital IC Testing Taxonomy of Testing • Fault Models • Test Pattern Generation • Output Response Analysis 85.2 Design for Test The Testability Problem • Design for Testability • Future for Design for Test 85.1 Digital IC Testing Micaela Serra In this section we give an overview of digital testing techniques with appropriate reference to material containing all details of the methodology and algorithms. First, we present a general introduction of terminology and a taxonomy of testing methods. Next, we present a definition of fault models, and finally we discuss the main approaches for test pattern generation and data compaction, respectively. Taxonomy of Testing The evaluation of the reliability and quality of a digital IC is commonly called testing, yet it comprises distinct phases that are mostly kept separate both in the research community and in industrial practice. 1. Verification is the initial phase in which the first prototype chips are “tested” to ensure that they match their functional specification, that is, to verify the correctness of the design. Verification checks that all design rules are adhered to, from layout to electrical parameters; more generally, this type of functional testing checks that the circuit: (a) implements what it is supposed to do and (b) does not do what it is not supposed to do. Both conditions are necessary. This type of evaluation is done at the design stage and uses a variety of techniques, including logic verification with the use of hardware description languages, full functional simulation, and generation of functional test vectors. We do not discuss verification techniques here. 2. Testing correctly refers to the phase when one must ensure that only defect-free production chips are packaged and shipped and detect faults arising from manufacturing and/or wear-out. Testing methods must (a) be fast enough to be applied to large amounts of chips during production, (b) take into consideration whether the industry concerned has access to large expensive external tester machines, and (c) consider whether the implementation of built-in self-test (BIST) proves to be advantageous. In BIST, the circuit is designed to include its own self-testing extra circuitry and thus can signal directly, during testing, its possible failure status. Of course, this involves a certain amount of overhead in area, and trade-offs must be considered. The development of appropriate testing algorithms and their tool support can require a large amount of engineering effort, but one must note that it may need to be done only once per design. The speed of application of the algorithm (applied to many copies of the chips) can be of more importance. Micaela Serra University of Victoria Bulent I. Dervisoglu Hewlett-Packard Company