counter lk-时钟 di2-2分频输出端 cIk div 2 di4-4分频输出端 diva div8-8分频输出端 div rary1eee 分频系数是2的整数次幂分频器的电路符号 use ieee std_logic_1164. all; use ieee std _logic_unsigned.all; entity counter 1s port(clk:in std_logic; div2 out std _logic;-2分频输出 div4 outsid logic;-41分频输出 div8: out std _logic);-:8分频输出 end counters architecture one of counter 1s signalcnt std _logic_vector(2 downto 0) B egin process(clk) if clk event and clk= hen +1; end if nd pr en rocess div 2<=cnt t(1);di8<=cnt(2; end one:分频系数是2的整数次幂分频器的电路符号 counter clk div2 clk –时钟 div2 – 2分频输出端 div4- 4分频输出端 div4 div8 div8- 8分频输出端 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(clk:in std_logic; div2:out std_logic; --2分频输出 div4:out std_logic; --4分频输出 div8:out std_logic); --8分频输出 end counter; architecture one of counter is signal cnt: std_logic_vector(2 downto 0); Begin process (clk) begin if clk’event and clk=‘1’ then cnt<=cnt+1; end if; end process; div2<=cnt(0);div4<=cnt(1);div8<=cnt(2); end one;